islet_rmm/rmi/rec/
vtcr.rs

1use crate::realm::rd::Rd;
2use crate::rec::Rec;
3use crate::rmi::error::Error;
4
5use aarch64_cpu::registers::*;
6
7fn is_feat_vmid16_present() -> bool {
8    #[cfg(not(any(miri, test)))]
9    let ret = ID_AA64MMFR1_EL1.read(ID_AA64MMFR1_EL1::VMIDBits)
10        == ID_AA64MMFR1_EL1::VMIDBits::Bits16.into();
11
12    #[cfg(any(miri, test))]
13    let ret = true;
14    ret
15}
16
17pub fn prepare_vtcr(rd: &Rd) -> Result<u64, Error> {
18    let s2_starting_level = rd.s2_starting_level();
19    let ipa_bits = rd.ipa_bits();
20
21    // sl0 consists of 2 bits (2^2 == 4)
22    if !(s2_starting_level >= 0 && s2_starting_level <= 3) {
23        return Err(Error::RmiErrorInput);
24    }
25
26    // t0sz consists of 6 bits (2^6 == 64)
27    if !(ipa_bits > 0 && ipa_bits <= 64) {
28        return Err(Error::RmiErrorInput);
29    }
30
31    let mut vtcr_val = VTCR_EL2::PS::PA_40B_1TB
32        + VTCR_EL2::TG0::Granule4KB
33        + VTCR_EL2::SH0::Inner
34        + VTCR_EL2::ORGN0::NormalWBRAWA
35        + VTCR_EL2::IRGN0::NormalWBRAWA
36        + VTCR_EL2::NSA::NonSecurePASpace
37        + VTCR_EL2::RES1.val(1); //XXX: not sure why RES1 is in default set in tf-rmm
38
39    if is_feat_vmid16_present() {
40        vtcr_val += VTCR_EL2::VS::Bits16;
41    }
42
43    let sl0_array = [
44        VTCR_EL2::SL0::Granule4KBLevel0,
45        VTCR_EL2::SL0::Granule4KBLevel1,
46        VTCR_EL2::SL0::Granule4KBLevel2,
47        VTCR_EL2::SL0::Granule4KBLevel3,
48    ];
49    let sl0_val = sl0_array[s2_starting_level as usize];
50    let t0sz_val = (64 - ipa_bits) as u64;
51
52    vtcr_val += sl0_val + VTCR_EL2::T0SZ.val(t0sz_val);
53
54    Ok(vtcr_val.into())
55}
56
57pub fn activate_stage2_mmu(rec: &Rec<'_>) {
58    VTCR_EL2.set(rec.vtcr());
59}
islet_rmm/rmi/rec/vtcr.rs

islet_rmm/rmi/rec/
vtcr.rs
