1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146

use super::timer;
use crate::gic;
use crate::rec::Rec;
use crate::rmi::error::Error;

use aarch64_cpu::registers::*;

#[repr(C)]
#[derive(Default, Debug)]
pub struct Context {
    pub gp_regs: [u64; 31],
    pub elr: u64,
    pub spsr: u64,
    pub sys_regs: SystemRegister,
    pub gic_state: GICRegister,
    pub timer: TimerRegister,
    pub fp_regs: [u128; 32],
}

pub struct RegOffset;
impl RegOffset {
    pub const PC: usize = 31;
    pub const PSTATE: usize = 32;
    pub const SCTLR: usize = 40;
}

pub fn set_reg(rec: &mut Rec<'_>, register: usize, value: usize) -> Result<(), Error> {
    match register {
        0..=30 => {
            rec.context.gp_regs[register] = value as u64;
            Ok(())
        }
        RegOffset::PC => {
            rec.context.elr = value as u64;
            Ok(())
        }
        RegOffset::PSTATE => {
            rec.context.spsr = value as u64;
            Ok(())
        }
        _ => Err(Error::RmiErrorInput),
    }?;
    Ok(())
}

pub fn get_reg(rec: &Rec<'_>, register: usize) -> Result<usize, Error> {
    match register {
        0..=30 => {
            let value = rec.context.gp_regs[register];
            Ok(value as usize)
        }
        RegOffset::PC => {
            let value = rec.context.elr;
            Ok(value as usize)
        }
        _ => Err(Error::RmiErrorInput),
    }
}

impl Context {
    pub fn new() -> Self {
        // Set appropriate sys registers
        // TODO: enable floating point
        // CPTR_EL2, CPACR_EL1, update vectors.s, etc..
        Self {
            spsr: (SPSR_EL2::D.mask << SPSR_EL2::D.shift)
                | (SPSR_EL2::A.mask << SPSR_EL2::A.shift)
                | (SPSR_EL2::I.mask << SPSR_EL2::I.shift)
                | (SPSR_EL2::F.mask << SPSR_EL2::F.shift)
                | (SPSR_EL2::M.mask & u64::from(SPSR_EL2::M::EL1h)) << SPSR_EL2::M.shift,
            ..Default::default()
        }
    }

    pub unsafe fn into_current(rec: &Rec<'_>) {
        TPIDR_EL2.set(rec as *const _ as u64);
        gic::restore_state(rec);
        timer::restore_state(rec);
    }

    pub unsafe fn from_current(rec: &mut Rec<'_>) {
        gic::save_state(rec);
        timer::save_state(rec);
    }
}

/// Generic Interrupt Controller Registers
#[repr(C)]
#[derive(Default, Debug)]
pub struct GICRegister {
    // Interrupt Controller Hyp Active Priorities Group 0 Registers
    pub ich_ap0r_el2: [u64; 4],
    // Interrupt Controller Hyp Active Priorities Group 1 Registers
    pub ich_ap1r_el2: [u64; 4],
    // GICv3 Virtual Machine Control Register
    pub ich_vmcr_el2: u64,
    // Interrupt Controller Hyp Control Register
    pub ich_hcr_el2: u64,
    // GICv3 List Registers
    pub ich_lr_el2: [u64; 16],
    // GICv3 Maintenance Interrupt State Register
    pub ich_misr_el2: u64,
}

#[repr(C)]
#[derive(Default, Debug)]
pub struct SystemRegister {
    pub sp: u64,
    pub sp_el0: u64,
    pub esr_el1: u64,
    pub vbar: u64,
    pub ttbr0: u64,
    pub ttbr1: u64,
    pub mair: u64,
    pub amair: u64,
    pub tcr: u64,
    pub tpidr: u64,
    pub tpidr_el0: u64,
    pub tpidrro: u64,
    pub actlr: u64,
    pub vmpidr: u64,
    pub csselr: u64,
    pub cpacr: u64,
    pub afsr0: u64,
    pub afsr1: u64,
    pub far: u64,
    pub contextidr: u64,
    pub cntkctl: u64,
    pub par: u64,
    pub vttbr: u64,
    pub esr_el2: u64,
    pub hpfar: u64,
    pub sctlr: u64,
}

#[repr(C)]
#[derive(Default, Debug)]
pub struct TimerRegister {
    pub cntvoff_el2: u64,
    pub cntv_cval_el0: u64,
    pub cntv_ctl_el0: u64,
    pub cntpoff_el2: u64,
    pub cntp_cval_el0: u64,
    pub cntp_ctl_el0: u64,
    pub cnthctl_el2: u64,
}